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SY89840U
Precision LVPECL Runt Pulse Eliminator 2:1 Multiplexer
General Description
The SY89840U is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89840U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique Fail-Safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV). The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The output is 800mV, 100K compatible LVPECL with fast rise/fall times guaranteed to be less than 190ps. The SY89840U operates from a 2.5V 5% or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89840U is (R) part of Micrel's high-speed, Precision Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* Selects between two sources, and provides a glitch-free, stable LVPECL output * Guaranteed AC performance over temperature and supply voltage: - Wide operating frequency: 1kHz to >1.5GHz - < 880ps In-to-Out tpd - < 190ps tr/tf * Unique patent-pending input isolation design minimizes crosstalk * Fail-safe input prevents oscillations * Ultra-low jitter design: - <1psrms random jitter - <1psrms cycle-to-cycle jitter - <10pspp total jitter (clock) - <0.7psrms MUX crosstalk induced jitter * Unique patent-pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS) * 800mV LVPECL output swing * 2.5V 5% or 3.3V 10% supply voltage * -40C to +85C industrial temperature range * Available in 16-pin (3mm x 3mm) MLFTM package
Applications
* Redundant clock switchover * Failsafe clock protection
Markets
* * * * LAN/WAN Enterprise servers ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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SY89840U
Typical Application
Simplified Example Illustrating RPE (Runt Pulse Elimination) Circuit when Primary Clock Fails
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SY89840U
Ordering Information(1)
Part Number SY89840UMG SY89840UMGTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel.
(2)
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 840U with bar-line Pb-Free indicator 840U with bar-line Pb-Free indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
16-Pin MLF
TM
(MLF-16)
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SY89840U
Pin Description
Pin Number 4, 1, 16, 13 Pin Name IN0, /IN0, IN1, /IN1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VT pin through 50 . Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the "Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01 F low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. See "Input Interface Applications" section. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Positive Power Supply: Bypass with 0.1 F//0.01 F low ESR capacitors as close to VCC pins as possible. Differential Outputs: This differential LVPECL output is a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details. Ground: Ground pin and exposed pad must be connected to the same ground plane. Power-On Reset (POR) Initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See "Power-On Reset (POR) Description" section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open.
3, 15
VT0, VT1
2, 14
VREF-AC0 VREF-AC1
10 5, 8, 12 6, 7 9
SEL VCC Q, /Q GND Exposed Pad
11
CAP
Truth Table
IN0 0 1 X X /IN0 1 0 X X INPUTS IN1 X X 0 1 /IN1 X X 1 0 SEL 0 0 1 1 OUTPUTS Q /Q 0 1 0 1 1 0 1 0
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SY89840U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................................-0.5V to +4.0V Input Voltage (VIN) .........................................................-0.5V to VCC
Storage Temperature (Ts) .......................................-65C to 150C
Operating Ratings(2)
LVPECL Output Current (IOUT) Continuous ............................................................ 50mA Surge ................................................................... 100mA
Termination Current Source/Sink Current on VT............................................100mA Source/Sink Current on IN, /IN .......................................50mA VREF-AC Current Source/sink current on VREF-AC .........................................2mA Lead Temperature (soldering, 20 sec.)................................. +260C
Supply Voltage (VCC)............................... +2.375V to +2.625V .................................................................. +3.0V to +3.6V Ambient Temperature (TA) ............................. -40C to +85C (3) Package Thermal Resistance MLFTM ( JA) Still-Air .................................................................. 60C/W MLFTM ( JB) Junction-to-Board................................................. 33C/W
DC Electrical Characteristics(4)
TA = -40C to +85C; unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIN (max) is specified when VT is floating.
JA
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Input Voltage Threshold that Triggers FSI IN-to-VT (IN, /IN) Output Reference Voltage
Condition
Min 2.375 3.0
Typ
Max 2.625 3.6
Units V V mA
No load, max VCC. 45 90 1.2 0 See Figure 1a. Note 5 See Figure 1b. 0.1 0.2
65 50 100
95 55 110 VCC VIH-0.1 VCC
V V V V
30
100 1.28
mV V V
VCC-1.3
VCC-1.2
VCC-1.1
and
JB
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SY89840U
LVPECL Outputs DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50
Symbol VOH VOL VOUT VDIFF-OUT Parameter Output HIGH Voltage Q, /Q Output Low Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q See Figure 1a See Figure 1b Condition
to VCC-2V, unless otherwise stated.
Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89840U
AC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50
Symbol fMAX tpd Parameter Maximum Operating Frequency Differential Propagation Delay In-to-Q In-to-Q SEL-to-Q SEL-to-Q tpd Tempco tSKEW tJitter Differential Propagation Delay Temperature Coefficient Part-to-Part Skew Random Jitter Cycle-to-Cycle Jitter Total Jitter (TJ) Crosstalk-induced Jitter tr, tf
Notes: 7. 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Propagation delay is measured with input tr, tf 300ps (20% to 80%) and VIL 800mV. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
to VCC-2V, unless otherwise stated.
Min 1.5 200mV 800mV
(8) (8)
Condition Clock 100mV < VIN 200mV < VIN
Typ 2.0 625 600
Max 880 820 17 900
Units GHz ps ps cycles ps fs/ C
o
480 460 550
RPE enabled, see Timing Diagram RPE disabled (VIN = VCC/2)
115 Note 9 Note 10 Note 11 Note 12 Note 13 At full output swing 70 130 200 1 1 10 0.7 190
ps ps(rms) ps(rms) ps(pp) ps(rms) ps
Output Rise/Fall Time (20% to 80%)
10. Random jitter is measured with a K28.7 character pattern, measured at 12
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SY89840U RPE and FSI Functionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" for more detailed information. Case #1 Two Normal Clocks and RPE Enabled In this case the frequency difference between the two running clocks IN0 and IN1 must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages. * Stage 1: The output will continue to follow CLK1 for a limited number of pulses. * Stage 2: The output will remain LOW for a limited number of pulses of CLK2. * Stage 3: The output follows CLK2.
Functional Description
RPE MUX and Fail-Safe Input The SY89840U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: Runt-Pulse Eliminator (RPE) Circuit: The RPE MUX provides a "glitchless" switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. Fail-Safe Input (FSI) Circuit: The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV differentially (VDIFF_IN), the output will latch to the last valid clock state.
Timing Diagram 1
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Micrel, Inc. Case #2 Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled). If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.
SY89840U Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. Stage 3: The output will follow CLK2
* *
*
Timing Diagram 2
Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.
Case #3 Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled). If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.
* *
Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. Stage 2: The output will follow CLK2.
Timing Diagram 3
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Micrel, Inc. Case #4 Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled). If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV (VIN) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending on the last valid state at the CLK1. If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI
SY89840U function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for more detailed information.
Timing Diagram 4
Power-On Reset (POR) Description
The SY89840U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 11) controls the delay for the power-on reset function. Calculation of the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V. The following equation describes this relationship: C(F)
t dPS ( ms ) 12( ms / F )
As an example, if the time required for the system power supply to power up past 2.3V is 12ms, the required capacitor value on pin 11 would be:
C(F) C(F)
12ms 12( ms / F )
1F
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SY89840U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, VIN 400mVpk, tr/tf 300ps, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY89840U
Singled-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
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SY89840U
Input Interface Applications
Option: may connect VT to VCC
Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface
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SY89840U
LVPECL Output Interface Applications
LVPECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100 controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 4a. Parallel Termination-Thevenin Equipment
Figure 4b. Parallel Termination (3-Resistor)
Part Number SY89841U SY89842U
Function Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer Precision CML Runt Pulse Eliminator 2:1 Multiplexer MLF
TM
Data Sheet Link www.micrel.com/product-info/products/sy89841u.shtml www.micrel.com/product-info/products/sy89842u.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
Application Note
HBW Solutions
New Products and Applications
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16 Lead (3mmx3mm) MicroLeadFrameTM (MLF-16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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